1. Field of the Invention:
This invention relates to non-volatile semiconductor memories and more particularly to metal nitride oxide semiconductor capacitors or transistors interconnected into an array.
2. Description of the Prior Art:
In the prior art, various non-volatile semiconductor memories have been described using metal nitride oxide semiconductor (MNOS) transistors. Normally, the source, drain and gate of the MNOS transistor are interconnected in an array of rows and columns with voltages applied to the gates of a selected row of transistors to read out the data stored in the transistor by monitoring the conductance or current flowing through the transistor. The information is stored in the MNOS transistor by applying a polarization voltage between the gate and body which causes charge to travel or tunnel into or out of the silicon nitride and silicon dioxide layer with respect to the body. The presence or absence of charge causes a shift in the threshold voltage V.sub.T of the transistor. If the MNOS transistor has a stepped gate oxide and is of the P channel type, then the transistor will be non-conducting when zero voltage is applied to the gate with respect to the body. In other words, the transistor stays in the enhancement mode due to thicker oxide regions adjacent the drain and source regions of the transistor. The enhancement mode region in MNOS N-channel transistors has a very limited threshold voltage region. In addition, the N-channel transistor has a large depletion mode region with respect to the threshold voltage. In the depletion mode, the N-channel transistor is conducting with zero volts on the gate. The various conducting transistors provide current paths which interfere with sensing the conductance of other transistors in the array.
One solution to utilizing an array of MNOS N-channel transistors is described in a publication entitled "A 16 K Bit Electrically Eraseable PROM Using N-Channel SI-Gate MNOS Technology" by Takaaki Hagiwara et al. which appeared in the IEEE Journal of Solid State Circuits, Vol. SC-15, No. 3, June, 1980 where the current passing through unselected N-channel transistors was controlled by placing in series with each transistor a second N-channel field effect transistor. FIG. 1A and 1B, for example, show an N-channel MNOS transistor in series with an N-channel MOS transistor to form a memory cell. The gate of the MOS transistors of a selected row is biased to turn the MOS transistor on which enables current to pass through both the MNOS transistor and the MOS transistor in its respective column to a sense amplifier. Of course, if the MNOS transistor is in the enhancement mode, no current will flow through it. The gate voltage of every MNOS transistor may remain at zero volts during read operation.
During write operation, the gates of the MNOS transistors of a selected row are raised to a voltage of V.sub.PP which may be, for example, +25 volts. The gates of unselected MNOS transistors are grounded. Writing is inhibited on selected MNOS transistors by placing 20 volts on the source. Writing is achieved on selected MNOS transistors by grounding the source. Thus, to write into the array as shown in FIG. 9 of the publication by Hagiwara et al, the appropriate circuit must operate at high voltages, 25 volts for V.sub.PP and 20 volts for the column inhibit lines. The gate electrodes of both the MNOS transistor and the MOS transistor as shown in FIG. 1A are of polysilicon material.
Instead of using two transistors per bit of storage, one for access and one for storage, an alternate arrangement has been described using one MOS transistor with a stepped oxide with the fixed threshold regions having a separate gate electrode from the gate electrode of the memory threshold region. Such an arrangement has been described in a publication entitled "The Gated-Access MNOS Memory Transistor" by H. A. Richard Wegener, which appeared in IEEE Transactions on Electron Devices, Vol. ED-27, No. 1, January, 1980, pages 266 through 276. The gated access transistor has a source region, fixed threshold region, a memory region, a fixed threshold region and a drain region. The oxide is thinnest in the memory or variable threshold region. The gate electrodes for the fixed threshold regions may be formed using a self-aligned silicon gate process. The transistor may be an N-channel depletion mode thereby providing a conducting or non-conducting channel in the memory region with zero volts on the memory gate. The memory gate may be aluminum. The fixed threshold regions are separately controlled during read operation to selectably detect the current or conduction through selected transistors. Thus, during read operation, the memory gates of all transistors may be held at zero volts. During write operation, a scheme is described where the write voltage is placed only on the memory gate only which is isolated by oxide from the substrate permitting it to be both positive and negative. A negative voltage on the memory gate causes positive charge to be stored in the memory gate dielectric. The fixed field effect regions together with the voltage on the source and drain region either place electrons underneath the memory region such as with zero volts on the source line or prevents electrons from entering beneath the memory region such as by putting positive ten volts on the source line. After all memory regions are preconditioned with electrons or no electrons underneath the memory region, a positive voltage is placed on the memory gate line such as +25 volts. For memory regions that contain electrons in the body of the transistor, the electrons are drawn into the dielectric and neutralize the positive stored charge thereby shifting the threshold voltage of the memory region. For memory regions containing no electronic charge in the body, no electrons are drawn into the dielectric and the positive charge previously stored is preserved. The advantage of having write voltages only on the memory gate line is that low voltage peripheral circuits to the array may be used.
It is therefore desirable to provide a non-volatile memory using an MOS N-channel field effect transistor and a MNOS device for storing charge and where information may be written and read out of the MNOS device by applying a sequence of pulses to the gate of the MNOS device.
It is further desirable to provide an array of non-volatile memory cells containing an N-channel MOS transistor and a MNOS device having an N-channel and wherein information may be written into and read out by capacitive coupling from the gate to the drain of the MNOS device.
It is further desirable to provide a non-volatile array comprised of MOS field effect transistors and MNOS devices coupled to each MOS field effect transistor wherein the MNOS device comprises a source, body, gate and gate dielectric of nitride and oxide which exhibits a variable threshold characteristic.
It is further desirable to provide a memory array of cells wherein the peripheral circuitry may be at low voltages during read operation such as five volts or less.
It is further desirable to provide a non-volatile memory comprising an array of cells, each cell having an MNOS device having a gate and source and gate dielectric exhibiting a variable threshold characteristic wherein all the gates may be coupled together and isolated from the substrate by a dielectric to permit positive and negative polarity voltages thereon.
It is further desirable to provide a non-volatile memory comprising an array of memory cells, each cell including an MNOS device wherein the entire array may be fabricated on bulk silicon or on silicon on sapphire.